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RemoteListed Jun 25, 2026

ASIC Architect

Quantum Dice

  • ASIC-Architecture
  • Computer-Architecture
  • Hardware-Engineering
  • Microelectronics
  • Principal-ASIC-Design-Engineer
  • Principal-ASIC-Engineer
  • RTL-Design
  • Senior-ASIC-Engineer

Assessed from original listing evidence

The role

Job description

About the Role

We are seeking an experienced candidate to lead the miniaturisation of our cutting-edge probabilistic computing platform. This role is to own the ASIC architecture of Quantum Dice's probabilistic computing processor end-to-end: from algorithm and ISA through partitioning, microarchitecture, and tape-out.

Key Responsibilities

  • Requirements analysis
  • System-level and algorithm understanding, HW/SW co-design: arithmetic implementation in hardware. Analysis of programmability, fixed functions, hardware implementation, and host requirements.
  • Functional simulation & building models to drive architectural decisions.
  • System-level architecture & ISA definition: turn workloads into system architecture and instruction set architecture / dataflow models.
  • Trade-off analysis (timing, power, area), own partitioning with physical design awareness
  • Detailed specifications for microarchitectures:
    • RTL requirements definition
    • Memory hierarchy
    • On-chip and inter-chip connectivity
    • Interfacing (analogue domain and software)
  • Overseeing internal IP development & 3rd party IP evaluation
  • Lead the design through verification, signoff, tape-out and bring-up.

Required qualifications

  • Architectural ownership of >= 1 ASIC taken to successful tape-out (preferably compute accelerator, inference engine, DSP)
  • Hands-on performance modelling (in Python, C++ or equivalent), trade-off analysis & simulation which drove your architectural decisions.
  • Industry tool flow experience (e.g. Synopsys, Cadence, or Siemens)
  • Solid grasp of timing, power and area trade-offs at the architectural level.
  • Experience defining HW/SW interfaces and working with firmware/compiler teams
  • Strong RTL design experience & defined verification strategies on architectural level

Why Join Us?

You’ll be at the forefront of next-generation computing, shaping a platform that redefines performance and efficiency. This is an opportunity to lead innovation in a rapidly evolving field.

Originally posted on Himalayas